A Particle Swarm Optimization Technique used for the Improvement of Analogue Circuit Performances

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Design and Implementation of A 6-GHz Array of Four Differential VCOs Coupled Through a Resistive Network

International audienceThis paper presents the design and the implementation of a fully monolithic coupled-oscillator array, operating at 6 GHz with close to zero coupling phase, in 0.25 μm BICMOS SiGe process. This array is made of four LC-NMOS differential VCOs coupled through a resistor. The single LC-NMOS VCO structure is designed and optimized in terms of phase noise with a graphical optimization approach while satisfying design constraints. At 2.5 V power supply voltage, and a power dissipation of only 125 mW, the coupled oscillators array features a simulated phase noise of -127.3 dBc/Hz at 1 MHz frequency offset from a 6 GHz carrier, giving a simulated phase progression that was continuously variable over the range -64° < Δphi <64 ° and -116° < Δphi < 116°. This constant phase progression can be established by slightly detuning the peripheral array elements, while maintaining mutual synchronization

Conception et implémentation d'un réseau composé de quatre VCOs couplés oscillant à 6 GHz

National audienceCe papier décrit la conception et l'implémentation d'un réseau d'oscillateurs couplés totalement intégré en technologie BiCMOS SiGe 0,25 μm. Ce réseau est constitué de quatre VCOs NMOS différentiels couplés au moyen d'une résistance. Pour une tension d'alimentation de 2.5V, une puissance consommée de 125 mW à une fréquence d'oscillation de 6 GHz, le réseau présente un bruit de phase de -127dBc/Hz à 1MHz de la porteuse et un déphasage qui varie de façon continue entre -64° et +64 ° et entre -116° et +116°

Graphical method for the phase noise optimization applied to a 6-GHz fully integrated NMOS differential LC VCO

International audienceThis paper describes the design and the optimization in terms of phase noise of a fully integrated NMOS Voltage Controlled Oscillator (VCO) using a 0.25 μm BICMOS SiGe process. A three-dimensional phase noise analysis diagram and a graphical optimization approach is presented to optimize the phase noise of the VCO while satisfying design constraints such as tank amplitude, power dissipation, tuning range and start up conditions. At 2.5 V power supply voltage, the optimized VCO features a simulated phase noise of -118 dBc/Hz at 1 MHz frequency offset from a 6.12 GHz carrier. The VCO is tuned from 6.1 GHz to 7.9 GHz with a tuning voltage varying from 0 to 2.5 V, and a power dissipation of only 7.4 mW

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

This paper presents the prediction of single-bit discrete-time feed-forward Delta-Sigma (DT FF ΔΣ) modulators performance for wireless standards with the use of two methods. The presented work uses the MAPLE tool and a new design automation tool to estimate the performance of different DT FF ΔΣ modulators topologies intended for low power consumption systems. The proposed tool is based on synthesis algorithm, which takes advantage of analytical models of both FF ΔΣ modulator and operational transconductance amplifier (OTA) performance. By defining the required specifications, the proposed synthesis tool is capable to find the predictive performance of both the modulator topology and the required OTA building block for future process. A Graphical User Interface is programmed to easily present some designed circuits examples

Étude de la technique des courants commutés. Application à la conversion analogique-numérique sigma-delta

After giving the basics of the switched-current technique as a principle of design of mixed electronic functions, the foundations of the sigma-delta based analog-digital conversion are explained: oversampling and noise shaping in the modulator following by decimation filter to obtain the expected resolution. Integrators are the centerpieces of the modulator; after describing possible solutions to perform this function, two original integrators are offered in which defects are compensated including charge injection. In the design, the simulation step, delicate problem for discrete-time circuits, is solved by two complementary approaches, one functional and the other behavioral. Finally achieving two second-order modulators are described, they can achieve resolutions of 9 and 10 bits. The second led to an analog to digital conversion chain of 12 bits.Après avoir donné les bases de la technique des courants commutés comme principe de conception de fonctions analogiques, les fondements de la conversion analogique-numérique Sigma-Delta sont expliqués : sur-échantillonnage avec mise en forme du bruit de quantification dans le modulateur puis obtention de la résolution souhaitée grâce au filtrage numérique à décimation. Les intégrateurs sont les pièces maîtresses du modulateur; après avoir décrit des solutions possibles pour réaliser cette fonction, deux intégrateurs originaux sont proposés dans lesquels les défauts sont compensés notamment l'injection de charge. Lors de la conception, l'étape de simulation, problème délicat pour les circuits à temps discret, est résolu par deux approches complémentaires, l'une fonctionnelle, l'autre comportementale. Enfin deux réalisations de modulateurs du second ordre sont décrites, elles permettent d'atteindre des résolutions de 9 et 10 bits. la seconde a donné lieu à une chaîne de conversion analogique-numérique sur 12 bits

Behavioral Study of a Second Order Sigma Delta Modulator Using Switched-Current Technique

International audienceIn this paper we present a method for the modelization of Sigma-Delta modulators using switched current technique for implementation. The purpose of this work is to allow behavioral study of modulators, taking account the main problem of this technique which is charge injection in MOS switches. The idea consists of a mathematical modeling of charge injection phenomena implemented on MATLAB software to analyze the distortion on modulator output spectrum. Simulation results using the proposed model are presented and compared with measurement results from designed modulator; it shows the efficiency of the model used and permits to analyze the effect of different levels of errors on the behaviors of Sigma-Delta modulato

Ultra-low-power wideband NMOS LC-VCO design for autonomous connected objects

International audienceIn this paper, a fully integrated subthreshold LC voltage controlled oscillator (VCO) is presented. A design methodology is also proposed to find the optimal parameters lowering the power consumption. This methodology has been applied to design oscillators for different frequency bands. Furthermore, an adaptive body biasing technique has been used to improve the startup constrains and allows a high immunity to PVT (process, voltage and temperature) variations. A VCO operating in 5 GHz ISM (Industrial, Scientific and Medical) band has been realized with the proposed methodology in 0.13μm CMOS. It consumes only 468 μW from 0.39V supply voltage. This makes it possible to meet the required specifications of autonomous connected objects and IoT applications. The measured oscillation frequency can be tuned from 5.14 GHz to 5.44 GHz. The obtained phase noise is approximately equal to-112 dBc/Hz in post-layout simulation (PLS) and-104.5 dBc/Hz in measure

A subthreshold low-power CMOS LC-VCO with high immunity to PVT variations

International audienceInternet of things is a topic of rising interest and intensive research, where power consumption is one of its most relevant challenges. This article presents a new radiofrequency subthreshold ultra low power LC voltage controlled oscillator (VCO). A graphical inductor optimization approach has been proposed and used to design the LC VCO leading to high performances in terms of power consumption, chip area and phase noise. It uses the adaptive body biasing technique to ensure high immunity to process, voltage and temperature variations. Realized in a 130 nm CMOS technology, the VCO occupies a total area of 0.234 mm(2). The measured frequency varies between 2.34 and 2.43 GHz. The post-layout simulation results show a phase noise of -116.1 dBc/Hz @1 MHz offset frequency, while the measured phase noise is -107.36 @1 MHz due to noisy measuring environment. The presented VCO provides a measured power consumption of only 168 mu W from 0.6 V supply voltage, making it suitable for ultra low power applications